-*-Outline-*- *mR_Slug's Chip-set Encyclopedia: _______________________________________________________ |\ _____ __ __ \ | \ \ __`\ \ \ __ mR_Slug's \ \__ \ \ \ \ \ \_\ \ \___ \_\ _____ ___ ___ \ _\ \ \ \ \ \ _ \ _ `\ \ \ \ __`\ ____ / ,_\ / __`\\ \ \ \ \ \ \_\ \ \ \ \ \ \ \ \ \_\ \\___\\__,`\\ __/ \ \_ \ \ \ \____/ \_\ \_\ \_\ \ __/ \___/ \____\ \__\ \ \ \ \ \ \ \ \ \_\ E n c y c l o p e d i a \ \ \ o v1.00 \ \ \______________________________________________________\ \ | __ __ __ __ __ __ __ __ __ __ __ | \|__\_\__\_\__\_\__\_\__\_\__\_\__\_\__\_\__\_\__\_\__\_\| | | | | | | | | | | | | | | | | | | | | | | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| Best viewed in emacs outline mode. \HTML Download: [chipsets-v1.00.txt.tar.gz] \HTML Old: [chipsets-v0.99.txt.tar.gz] Warning! This file wont fit on a 1.44MB floppy, use 2.88MB or floptical Since you are here, I'm assuming the most likely method you've used to access this website is on an ASR-33 (or equivalent) terminal connected to some *nix box using the linemode browser. Other user-agents are also supported. **DISCLAIMER! THE DOCUMENT IS PROVIDED "AS IS", WITH ABSOLUTELY NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE DOCUMENT OR THE USE OR OTHER DEALINGS IN THE DOCUMENT. ***More Disclaimers: This document also contains quotes from manufactures data- sheets. That include similar disclaim of all warranties. See the datasheets. Also note that the manufacturer's information is sometimes wrong, although often the best source. *Search: If in emacs at any time type M-< C-s (M = Alt, C = Ctrl.) **IsIndex based search In a web browser you can use isindex. type the term and press return: \HTML **Form based search (requires the new HTML 2.0) On more modern browsers supporting HTML 2.0 you can now use forms: \HTML Form Search:
                      
*Read Me/FAQ/General Info **Intro: The information contained within this file should not be considered 100% correct. Where possible information has been taken from datasheets, however even this info may be incorrect. The datasheets state what the chip should do, not what they actually do. This is, compounded further by different revisions of chips. This document will never be complete, and I have no intention of finding every datasheet for every chip set. Some of the chip sets listed are from later systems in the PIII/P4/Athlon era. There are many websites with information on these chip sets and these entries will likely not be expanded upon. The focus of this document is early PC/XT to Pentium chip sets. There are few sites that clearly illu- strate this information, and how they relate to each other. I aim to prioritize cataloging significant, rare or otherwise interesting chip sets. The reason I wrote all of this down, is so that I could FORGET it. Basically I needed to free up some RAM. I've a head full of arcane snippets of information on this subject. I don't want to end up a crazy old man ranting random disjointed information ("The C&T CS8220 came before the CS8221 you KNOW!") to disinterested passersby, unable to see how senile I've become. A side benefit, this might be useful to someone else:-) **Quote style: To avoid thousands of quote marks and colliding with quote marks in the text, I have used a modified quotation style. Anything in a section titled "Info:" or "Features:" is a quote from a datasheet unless otherwised stated in that section. In these sections anything inside [] is an annotation and not part of the datasheet unless otherwise stated in that section. Under any other section, the text is my own unless indicated with "". Also this document does not contain the entire datasheet for each chip, usually only the first few pages are included to give an outline of it. Some datasheets are 100s of pages other are only 1. **Cant find a chip? Early chip sets have a title and a part no. to refer to the chip set as a whole. As time went on the chip set became one chip, so later chip sets are usually referred to by the part no. on the actual chip. These are usually called "Single Chip" by the manufacture, although they nearly always follow the 2-chip North/South-bridge paradigm. So these are referred to by for example, "M1521/M1523" or "M1521/M23" for short. If there is a part number for the chip set as a whole that has precedence. Try the search function for a chip part no. and hopefully it will turn up the chip set it was part of. **Why this document is not GPL or a wiki The document is copyright, it is NOT GPL'ed text. While the GPL is a fantastic idea, I have chosen not to make this freely copied and modified. The reasons are as follows: 1. GPL text tends to be copied...EVERYWHERE. For example, if you look up a subject on wikipedia, then try to get more information, or a different perspective on say about.com. There you find the EXACT SAME TEXT. This is what mirrors are for. It's an unintended consequence, but it can lead to misinformation being spread everywhere. A bigger problem. 2. There seems to be fewer and fewer informative websites. It used to be that if you searched for something you would find a website about a particular subject. Now you tend to find the encyclopedia and often nothing else (well quickly). In addition the majority of this text is quotes. The wiki concept is a good idea, but they have problems. Because no one "owns" the work they seem to go to two extremes. Either no one maintains them, or there are edit wars. Also anyone can edit them. **Definition of a chip set: In short it is a set of chips that allow a system designer to build a computer. If we restrict the term 'chip' to that of a microchip then technically any microcomputer contains a chip set, even one based of 7400-series logic alone. In the context of this document, a chip set is defined as any group of chips used to implement an IBM or IBM-compatible PC/XT/AT/386/486/etc system. There are 2 main categories that these chips fall into: 1. Direct copies or re-implementations of Intel chips 2. Chip sets sold as a set of chips to implement an IBM-compatible that differ in some way to those used in an IBM system, e.g. not pin compatible. An example of the former would be some early chips built by VLSI Technology (at the time known as VTI, to implement a 286: o VL82C37A is a: 82C37A DMA controller o VL82C59A is a: 82C59A interrupt controller o VL82C54A is a: 82C54 timer o VL82C612 is a: 74LS612 memory mapper o VL82C84A is a: 82284 clock generator and ready interface o VL82C88 is a: 82288 bus controller These are all direct replacements for the parts used in an IBM AT. Many companies had compatible versions of these chips. An early example of the latter is the Chips & Technology NEAT chip set: o 82C211 CPU/Bus controller, o 82C212 Page/Interleave and EMS Memory controller, o 82C215 Data/Address buffer o 82C206 Integrated Peripherals Controller (IPC). The description does not map directly to the parts used in the IBM AT. Later chip sets are often even more integrated sometimes consisting of just one chip, although two seems to be the most common. The latter is generally considered the definition of a chip set, and the former is not generally considered a chip set per-se. However when looking at the early chip sets this distinction can be very slight. Because of this, sets of chips meeting the criteria for (1.) have been included where possible. **'chip set', 'chip-set' or 'chipset'? I don't know, all seem to be ok/OK/okay. CHIPset is a term used by C&T. **What's not included: All information included in this file can be referenced to some document or picture. Or at least should be:-) As a result of this, proprietary chip sets, and odd combinations of different chip sets are not usually included. There tends to be scant information on proprietary chip sets, i.e. no datasheet. Similarly chip sets built using some components from one manufacture and some from another are kind of difficult to deal with. An example I know of is a 25 MHz 386 DX motherboard that uses the Intel N82230/N82231 (formerly, ZyMOS) 286 chip set, with an AUStek cache Controller. I know it existed but there is no documentation. So the best I can say you'll have to take my word that it existed. I can't include it because there is no real information there. Also not included is anything that isn't a PC-compatible chip set. I.e. no Macintosh info. Any Information on PC-incompatibles/ pseudo-compatibles, and other weirdi-type stuff I have a particular interest in. See the section: 'Info needed on'. Some information on video chip sets is included, occasionally but the focus is on motherboard implementation. **Who made the first chip set? By the criteria of (2.) in 'Definition of a chip set' many sources state this to be the Chips and Technologies NEAT chip set. I don't know why this is stated as it is most definitely incorrect. The CS8221 NEW Enhanced AT (NEAT) chip set consisting of the chips; 82C211/82C212/82C215/82C206 was as far as I can establish, first released sometime in 1986. C&T itself have an earlier chip set called the CS8220 PC/AT compatible Chip Set, and consists of the following chips; 82C201/82C202/ 82A203/82A204/82A205. It was first available in OCT-85. (see:C&T> CS8220>Notes for further info.) That is, AFAIK, the first motherboard chip set from C&T and AFAIK the worlds first chip set that meets the criteria of (2.). However C&T did already have on the market their popular EGA chip set, but that isn't a motherboard chip set. By the criteria of (1.), IBM, or Intel, see IBM>PC/XT chip set. Another pre-'86 chipset is the Faraday FE2010. The datasheet includes a schematic on the very last page dated 11/22/85. This only indicates the chip set was on paper at that date. An acutal release date has not been found. Faraday also makes the claim to be the first company to use VLSI tech. on a PC motherboard, the FE6410 (c:1983). This is however is a just a floppy controller, which pushes the definition of a chip set for pre-'86, more a peripheral. **Spelling errors/mistyped words Yes, I know there are spelling errors, and things are mistyped. It seems no matter how hard I try my fingers hit 't' twice when typing 'compatible' rendering it 'compattible' numerous, (thousands actually) times. I don't have the time or the will to check the spelling of everything. Basic spell checking has been peformed. Please let me know if there is anything that would lead to incorrect information, or something is so mangled that it needs revising. But if you can basically understand what was intended, just cope with it. Just cope:-) BTW, "110" port is an "I/O" port that has been OCRed badly, as is an "1/0" port. **Info needed on: Columbia Data Products first implementation AT&T 6300/M24 Compaq Portable implementation Compaq Deskpro 386 PS/2 model 30 **A note on VESA support of 486 chipsets. Many chipsets state that they support VESA local bus. In some cases these actually implement VLB somewhat like PCI, where it is entirly decoupled from the CPU bus. Chipsets that do not state they work with VLB, may be found on motherboards that contain VLB slots. VLB is *basically* The 486 CPU pinout in a slot form. Unless these m/boards contain some additional chips, there VLB implementation is directly coupled to the CPU. **Datasheets: See: \HTML http://108.59.254.117/~mR_Slug/pub/datasheets/chipsets/ Regetfully I did not keep them all. *_IBM **IBM PC/XT/AT See the Intel section *ACC Micro **Datasheets: See: ./datasheets/ACC_Micro/ **Notes: ACC Microelectronics Corporation Auctor Corporation is associated with this name. **ACC82010 AT Chip Set (286 12.5/16MHz Max) c88 ***info: ****General: The ACC 82010 is an integrated high performance CMOS chip set that replaces most of the MSI/SSI The ACC 82010 is an integrated high performance CMOS chip set that replaces most of the MSl/SSI logic used to build IBM PC/AT compatible systems. The first chip, the ACC 2000, is a peripheral controller that performs the functions of two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74L8612 memory mapper as well as other standard control logic circuitry. The second chip, the ACC 2100, is a system controller containing one 82284 clock generator, one 82288 bus controller, and a high performance memory controller providing 12.5 MHz or 16 MHz Operation as well as the standard AT mode with zero and one wait state schemes. The ACC 2220 is a buffer/latch chip that runs in two modes: data mode and address mode. The ACC 82010 chip set can support a 12.5/16MHz system clock design while maintaining 8 MHz AT bus compatibility. All chips in the ACC 82010 chip set are implemented using advanced CMOS technology and packaged in standard 84-L PLCC packages. The chip set's high integration reduces total system cost through lower power requirements, increased reliability, and reduced board size. ****ACC 2000 Multifunctional Peripheral Controller: The ACC 2000 is an integrated high performance CMOS PC/AT peripheral controller that incorporates several TTL, SSI, and MSI including two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74L8612 memory mapper. The ACC 2000 is a high performance VLSl that offers a single chip solution for all the peripherals attached to the X BUS (peripheral bus) in IBM PC/AT compatible systems. ****ACC 2100 System Bus Controller: The ACC 2100 is an integrated high performance CMOS PC/AT system controller that integrates the following functions and logic into one single chip: clock generator and selector, bus controller, bus swap logic, coprocessor interface logic, memory decoder, command delay and wait state generation circuits, reset and shut down logic, and ADDR/DATA control logic. ****ACC 2220 Data Buffers or Address Buffers: The ACC 2220 is a high performance buffer chip, running in two different modes. It activates the data buffers and latches mode when pin 25 is asserted low and the address buffers and latches mode when pin 25 is asserted high. ***Configurations: ACC 2000 Multifunctional Peripheral Controller ACC 2100 System Bus Controller ACC 2220 Data Buffers or Address Buffers (x2) 2000 + 2100 + 2220 (x2) Variants: According to the datasheet the max speed is 12.5MHz. It also states the max speed is 16MHz. Perhaps an early version is 12.5MHz, later upgraded to 16 MHz. YMMV ***Features: ****General: o 100% hardware and software compatible with the IBM PC/AT o Fully compatible with Intel 8237 DMA controller Intel 8259 interrupt controller Intel 8254 timer/counter Intel 82284 clock generator Intel 82288 bus controller Tl 74L8612 memory mapper o Functions include 7 DMA channels 3 timer/counter channels 14 external interrupt channels Data Buffers Address Buffers o Built in Refresh Control circuit o Supports up to 12.5 MHz system clock with zero wait state capability o I/O (8 MHz) AT BUS compatible o Supports 16 MB DMA address space o Built-in memory address decoder to support 1MB or 640KB o Wait state generation o 1.5 micron high performance CMOS technology o TTL compatible o Standard 84-L PLCC package ****ACC 2000 Multifunctional Peripheral Controller: o 100% hardware and software compatible with the IBM PC/AT o Fully compatible to Intel‘s 8237 DMA controller 8254 Timer/Counter 8259 Interrupt controller o Fully compatible to Tl's 74LS612 memory mapper o Supports 7 DMA channels, 3 timer/counter channels and 14 interrupt request channels o 100% compatible with the IBM AT I/O BUS o Supports up to 8 MHz DMA clock o Supports 16 MB DMA address space o Built-in refresh control circuit o TTL compatible o Speed switching through hardware or software o 1.5 micron high performance CMOS technology o 84-L PLCC package ****ACC 2100 System Bus Controller: o 100% hardware and software compatible with the IBM PC/AT o Fully compatible with Intel's 82284 clock generator, and 82288 bus controller o Built-in 80287 coprocessor interface logic o Built-in command delay and wait state generation logic o ROM chip select for 27128 or 27256 o Built-in memory controller o Turbo speed change performed through hardware or software o 8 MHz I/O AT BUS compatible o Bus swap function o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package ****ACC 2220 Data Buffers or Address Buffers: o 100% hardware and software compatible to the lBM AT o Data buffers and latches mode o Address buffers and latches mode o Built-in parity generation/detection logic o Built-in bus conversion logic for 16-bit to 8-bit transfers o Supports direct high drive for expansion slots o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package **ACC82020 Turbo PC/AT Chip Set (286/386SX 25MHz Max) c88 ***Notes: See the Notes: section of the ACC82021 section. ***info: ****General: The ACC 82020 is an integrated high performance CMOS chip set that replaces most of the MSl/SSI logic used in building an IBM PC/AT compatible system. The first chip, the ACC 2000, is a peripheral controller that performs the functions of two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74L8612 memory mapper as well as other standard control logic circuitry. The second chip, the ACC 2120, is a system controller containing one 82284 clock generator, one 82288 bus controller, and a high performance memory controller providing up to 25 MHz Operation as well as the standard AT mode with zero and one wait state schemes. To support a 16 MHz page interleaved operation with a 0.7 wait state, 100 ns memory can be used. The ACC 2220 is a data and address buffer/ latch chip that runs in two modes. This chip is used twice, one chip is the data buffer, the other is the address buffer/latch. The ACC 82020 chip set supports a system clock design up to 25 MHz while maintaining 8 MHz AT bus compatibility. All chips in the ACC 82020 chip set are implemented using advanced CMOS technology. The chip set’s high integration reduces total system cost through lower power requirements, increased reliability, and reduced board size. ****ACC 2000 Multifunctional Peripheral Controller: The ACC 2000 is an integrated high performance CMOS PC/AT peripheral controller that incorporates several TTL, 881, and MSI including two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74L8612 memory mapper. The ACC 2000 is a high performance VLSI that offers a single chip solution for all the peripherals attached to the X BUS (peripheral bus) in IBM PC/AT compatible systems. ****ACC 2120 System Bus Controller and Memory Controller: The ACC 2120 is an integrated high performance CMOS PC/AT system controller that integrates the following functions and logic into one single chip: clock generator and selector, bus controller, bus swap logic, coprocessor interface logic, memory decoder, command delay and wait state generation circuits, reset and shut down logic, and ADDR/DATA control logic. ****ACC 2220 Data Buffers or Address Buffers: The ACC 2220 is a high performance buffer chip, running in two different modes. It activates data buffers and latches mode when pin 25 is asserted low and address buffers and latches mode when asserted high. ***Configurations: ACC 2000 Multifunctional Peripheral Controller ACC 2120 System Bus Controller and Memory Controller ACC 2220 Data Buffers or Address Buffers (x2) 2000 + 2120 + 2220 (x2) Variants: The ACC 2120 has some additional features added "fourth quarter 1989" according to the datasheet. No info given to an updated part no. But see the Notes: section of the ACC82021 section. ***Features: ****General: o 100% hardware and software compatible with the IBM PC/AT o Fully compatible with Intel 8237 DMA controller Intel 8259 interrupt controller Intel 8254 timer/counter Intel 82284 clock generator Intel 82288 bus controller Tl 74L8612 memory mapper o Functions include 7 DMA channels 3 timer/counter channels 14 external interrupt channels Data buffers Address buffers o Supports Intel 286 and 386SX microprocessors o Supports Intel 287 and 387SX coprocessors o Supports chip select for mouse, hard disk, serial/parallel ports o Optional Direct Memory Access mode** o Supports 64K x 1, 256K x 1, 256K x 4, 1M x1,1M x4, 4M x1 memory and 16MB on motherboard o Supports single module of 1M x 9 DRAM o Supports remapping of 640K through 1M memory range o 4-Way or 2-way page interleaved memory controller o Supports EMS 4.0 o Built-in staggered memory refresh control o Supports up to 25 MHz system clock o I/O (8 MHz) AT BUS compatible o Quick hardware and software switch from protected mode to real mode for 08/2 optimization o Shadow RAM for BIOS >**Will be Available fourth quarter 1989 ****ACC 2000 Multifunctional Peripheral Controller: o 100% hardware and software compatible with the lBM PC/AT o Fully compatible to Intel's 8237 DMA controller 8254 Timer/Counter 8259 Interrupt controller o Fully compatible to Tl's 74L8612 memory mapper o Supports 7 DMA channels, 3 timer/counter channels and 14 interrupt request channels o 100% compatible with the IBM AT I/O BUS o Supports up to 8 MHz DMA clock o Supports 16 MB DMA address space o Built-in refresh control circuit o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package ****ACC 2120 System Bus Controller and Memory Controller: o 100% hardware and software compatible with the IBM PC/AT o Supports Intel's 286 and 386SX microprocessors o Built-in 80287 and 80387SX coprocessor interface logic o Fully compatible with Intel’s 82288 bus controller o Built-in command delay and wait state generation logic o Supports CPU operation up to 25 MHz o Supports 16 MB on board memory o Turbo speed change performed through hardware or software o 1-Way, 2-Way or 4-Way page interleaved memory controller o Optional Direct Access Memory Controller** o Simultaneous EMS and Shadow RAM** o Simultaneous extended and EMS expanded memory o Optional Direct Memory Access mode** o Supports 64K x 1, 256K x 1, 256K x 4, 1M x 1, 1M x 4, 4M x 1 memory and 16 MB on motherboard o 384K Memory mapping above the resident RAM address space o 512K Memory Mapping above the resident RAM address space** o Supports shadow RAM for efficient BIOS execufion o Programmable wait states for ROM o ROM chip select for 27256 or 27512 o Built-in OS/2 optimization circuitry o Supports EMS 4.0 address translation logic with 4 map registers o Staggered memory refresh o 1.2 micron high performance CMOS technology o 160-pin PFP package >**Available fourth quarter 1989 ****ACC 2220 Data Buffers or Address Buffers: o 100% hardware and software compatible to an IBM PC/AT o Data buffers and latches o Address buffers and latches o Built-in parity generation/detection logic o Built-in bus conversion logic for 16-bit to 8-bit transfers o Generates chip select for hard disk, floppy disk, serial and parallel ports o Supports direct high drive for expansion slots o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package **ACC82021 Turbo PC/AT Chip Set (286/386SX 25MHz Max) >88 ***Notes: The datasheet for this chip set only gives the general section. The 2121 chip has a separate datasheet. The 2000 and 2220 chip's information is sourced from the ACC82020 datasheet. The main difference between the ACC82020 and the ACC82021 is that the ACC82021 uses the ACC2121 System/Memory controller instead of the ACC2120. The ACC2120 chip lists some features as "Available fourth quarter 1989". It would appear that nearly all the features listed in this way are now in the ACC2121. Perhaps the ACC2120 chip was never updated and instead replaced by the ACC2121. Other features in the general section that differ are: Differences: Video BIOS shadowed Lists Chip select for floppy instead of mouse ***info: ****General: The 82021 is an integrated high performance CMOS chip set that replaces most of the MSl/SSI logic used in building an IBM PC/AT compatible system. The first chip, the 2000, is a peripheral controller that performs the functions of two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74LS612 memory mapper as well as other standard control logic circuitry. The second chip, the 2121, is a system controller containing one 82284 clock generator, one 82288 bus controller, and a high performance memory controller providing up to 25 MHz Operation as well as the standard AT mode with with page interleaved or direct access schemes. To support a 16 MHz page interleaved operation with a 0.7 wait state, 100 ns memory can be used. The 2220 is a data and address buffer/ latch chip that runs in two modes. This chip is used twice, one chip is the data buffer, the other is the address buffer/latch. The 82021 chip set supports a system clock design up to 25 MHz while maintaining 8 MHz AT bus compatibility. All chips in the 82021 chip set are implemented using advanced CMOS technology. The chip set's high integration reduces total system cost through lower power requirements, increased reliability, and reduced board size. ****ACC 2000 Multifunctional Peripheral Controller: The ACC 2000 is an integrated high performance CMOS PC/AT peripheral controller that incorporates several TTL, 881, and MSI including two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74L8612 memory mapper. The ACC 2000 is a high performance VLSI that offers a single chip solution for all the peripherals attached to the X BUS (peripheral bus) in IBM PC/AT compatible systems. ****ACC 2121 System Bus Controller and Memory Controller: The 2121 is an integrated high performance CMOS PC/AT system controller that integrates the following functions and logic into one single chip: clock generator and selector, bus controller, bus swap logic, coprocessor interface logic, memory decoder, command delay and wait state generation circuits, reset and shut down logic, and ADDR/DATA control logic. ****ACC 2220 Data Buffers or Address Buffers: The ACC 2220 is a high performance buffer chip, running in two different modes. It activates data buffers and latches mode when pin 25 is asserted low and address buffers and latches mode when asserted high. ***Configurations: ACC 2000 Multifunctional Peripheral Controller ACC 2121 System Bus Controller and Memory Controller ACC 2220 Data Buffers or Address Buffers (x2) 2000 + 2121 + 2220 (x2) ***Features: ****General: o 100% hardware and software compatible with the IBM PC/AT o Fully compatible with Intel 8237 DMA controller Intel 8259 interrupt controller Intel 8254 timer/counter Intel 82284 clock generator Intel 82288 bus controller Tl 74L8612 memory mapper o Functions include 7 DMA channels 3 timer/counter channels 14 external interrupt channels Data buffers Address buffers o Supports Intel 286 and 386SX microprocessors o Supports Intel 287 and 387SX coprocessors o Supports chip select for floppy, hard disk, serial/parallel ports o Optional Direct Memory Access mode o Supports 64K x 1, 256K x 1, 256K x 4, 1M x1,1M x4, 4M x1 memory and 16MB on motherboard o Supports remapping of 640K through 1M memory to above the resident RAN address space o 4-Way or 2-way page interleaved memory controller o Supports EMS 4.0 o Built-in staggered memory refresh control o Supports up to 25 MHz system clock o I/O (8 MHz) AT BUS compatible o Quick hardware and software switch from protected mode to real mode for 0S/2 optimization o Shadow RAM for system BIOS and video BIOS ****ACC 2000 Multifunctional Peripheral Controller: o 100% hardware and software compatible with the lBM PC/AT o Fully compatible to Intel's 8237 DMA controller 8254 Timer/Counter 8259 Interrupt controller o Fully compatible to Tl's 74L8612 memory mapper o Supports 7 DMA channels, 3 timer/counter channels and 14 interrupt request channels o 100% compatible with the IBM AT I/O BUS o Supports up to 8 MHz DMA clock o Supports 16 MB DMA address space o Built-in refresh control circuit o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package ****ACC 2121 System Bus Controller and Memory Controller: o 100% hardware and software compatible with the IBM PC/AT o Supports Intel's 286 and 386SX microprocessors o Built-in 80287 and 80387SX coprocessor interface logic o Fully compatible with Intel's 82288 bus controller o Built-in command delay and wait state generation logic o Supports CPU operation up to 25 MHz o Supports 16 MB on board memory o Turbo speed change performed through hardware or software o 1-Way, 2-Way or 4-Way page interleaved memory controller o Direct Access Memory Controller o Simultaneous EMS and Shadow RAM o Simultaneous extended and EMS expanded memory o Supports 64K x 1, 256K x 1, 256K x 4, 1M x 1, 1M x 4, 4M x 1 memory and 16 MB on motherboard o 384K Memory mapping above the resident RAM address space o Supports shadow RAM for efficient BIOS execution o Programmable wait states for ROM o ROM chip select for 27256 or 27512 o Built-in OS/2 optimization circuitry o Supports EMS 4.0 address translation logic with 4 map registers o Staggered memory refresh o 1.2 micron high performance CMOS technology o 160-pin PFP package ****ACC 2220 Data Buffers or Address Buffers: o 100% hardware and software compatible to an IBM PC/AT o Data buffers and latches o Address buffers and latches o Built-in parity generation/detection logic o Built-in bus conversion logic for 16-bit to 8-bit transfers o Generates chip select for hard disk, floppy disk, serial and parallel ports o Supports direct high drive for expansion slots o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package **ACC82300 386 AT Chip Set (386DX) c88 ***Info: ****General: The ACC 82300 chip set is designed for system designers to build a high performance 20/25 MHz 386 systems. The ACC 82300 contains three VLSl chips that can implement a 100% compatible IBM PC/AT system. The ACC 2500 provides system control signals, the ACC2300 is a page interleaved memory controller, and the ACC 2000 is the integrated peripherals controller. The ACC 82300 chip set supports a local CPU bus, a system memory bus, and compatible AT buses. The AT bus clock is fixed at 8 MHz and is totally asynchronous to the CPU clock to support compatible AT bus timing. The ACC 82300 chip set operates up to 20/25 MHz with zero wait state memory access by using 80ns DRAMs General Description The 82300 chip set is designed for 80386 based IBM PC/AT compatible systems. The 82300 supports four buses as illustrated in the system block diagram [see datasheet]. CPU local bus (A and D) is the bus between the 80386, and address and data buffers. DRAM is accessed through the system memory bus (MA and ID) and controlled by the ACC 2300. The I/O channel bus (SA and SD) is compatible with the IBM PC/AT bus and can support both 8-bit and 16-bit devices. The peripheral bus (PA and PD) interfaces the on-board DMA controller, timer, and interrupt controller. The local data bus and system memory data bus has a 32-bit data width. The I/O data bus supports up to 16 bits and the peripheral data bus supports 8-bit peripherals. ****ACC 2000 PC/AT integrated Bus & Peripheral Controller: The ACC 2000 is an integrated high performance CMOS PC/AT peripheral controller that incorporates several TTL, SSI, and MSI including two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, and one 74L8612 memory mapper. The ACC 2000 is a high performance VLSI that offers a single chip solution for all the peripherals attached to the X BUS (peripheral bus) in IBM PC/AT compatible systems. ****ACC 2300 Page/Page Interleaved Memory Controller: The ACC 2300 is an integrated high performance CMOS Memory Controller for an 80386 based system. The ACC 2300 performs in two modes: the Page/Page Interleaved mode, or the Direct Access mode. The memory configurations in either mode can be one bank (non-interleaved) or multiple banks (2 or 4) interleaved. This flexible configuration supports up to 16 MB of DRAMs with 1 Mbit DRAMs. With the ACC 2500 and the ACC 2000, the complete 386 chip set offers a 100% PC/AT compatible integrated solution for designers to build a powerful 20/25 MHz 386 workstation. ****ACC 2500 System Controller: The ACC 2500 is an integrated high performance CMOS System Controller for an 80386 based computer. The ACC 2500 provides the state machines that control all bus accesses and produces the control signals to interface with the 80386. The ACC 2500 has clock switching capability to run the processor at full speed or at an optional speed to accommodate application software. AT bus state machines control AT bus command timing for 100% compatibility with an IBM PC/AT. With the ACC 2300 and the ACC 2000, the complete 386 chip set offers a 100% PC/AT compatible integrated solution, and allows designers to build a powerful 20/25 MHz 386 work station. ***Configurations: ACC 2000 PC/AT integrated Bus & Peripheral Controller ACC 2300 Page/Page Interleaved Memory Controller ACC 2500 System Controller ***Features: ****General: o 100% IBM PC/AT compatible o Supports up to 16 MB on-board memory o Operates with Page interleaved DRAM accessing o Supports 1, 2 and 4 memory banks with 256K x 1 and 256K x 4, or 1M x 1 DRAMs o Supports 80387 coprocessors o Supports EMS 4.0 o Supports shadow RAM for efficient BIOS execufion o Independent AT bus clock o Flexible architecture to design customized 386 systems o Supports 20/25 MHz zero wait state operation ****ACC 2000 PC/AT integrated Bus & Peripheral Controller: o 100% hardware and software compatible with the lBM PC/AT o Fully compatible to Intel's 8237 DMA controller 8254 Timer/Counter 8259 Interrupt controller o Fully compatible to TI's 74L8612 memory mapper o Supports 7 DMA channels, 3 timer/counter channels and 14 interrupt request channels o 100 % compatible with the IBM AT I/O BUS o Supports up to 8 MHz DMA clock o Supports 16 MB DMA address space o Built-in refresh control circuit o TTL compatible o Speed switching through hardware or software o 1.5 micron high performance CMOS technology o 84-L PLCC package ****ACC 2300 Page/Page Interleaved Memory Controller: o High performance Page interleaved or Direct DRAM accessing o Flexible memory configurations of 1, 2, and 4 banks by using either 256K x 1 and 256K x 4, or 1M x1 DRAMs o Automatic remapping of the RAM in 512K (640K) to 1 MB address space o Staggered refresh to reduce power supply noise o Shadow RAM for efficient BIOS execution o Supports up to 16 MB on-board memory o Supports 20 MHz zero wait state by using 80 ns 256K x1 or 100 ns 256K x 4 or 100 ns 1M x 1 Fast Page mode DRAMs in Page mode o Supports 25 MHz zero wait state by using 80 ns 256 x 4 or 1M x1 DRAMS in Page interleaved mode o 100-pin PFP package ****ACC 2500 System Controller: o Independent 8 MHz AT Bus Clock o 20/25 MHz or 8 MHz processor clock selection o CPU interface and BUS control o AT Bus timing emulation o Reset and shut down logic o 100-pin PFP package **ACC82C100 Single-Chip PC/XT Systems-Controller c90 ***Info: The 82C101 is a high performance CMOS PC/XT bus and peripheral controller for designers to build a PC BUS-compatible single-board computer with "turbo" power, The 82C101 replaces all TTL/SSI/ MSI devices including six Intel peripheral controller ICs required to build a typical "Turbo XT." The 82C101 integrates all the controller functions of a typical "Turbo/XT" high performance motherboard. This high integration not only increases system performance but also reduces the total system cost because of lower power requirements, increased reliability, and reduced components and board size. ***Configurations: 82C101 ***Features: o 100% hardware and software compatible with IBM PC/XT o Fully compatible with Intel's 8284 Clock Generator 8288 Bus Controller 8237 DMA Controller 8259 Interrupt Controller 8254 Timer/Counter 8255 compatible peripheral I/O port o Built-in parity generator and checker, wait state logic, and NMI control logic o Supports EMS o Supports Shadow RAM o Supports low operating frequency for power-saving feature o Supports 8 MHz and 10 MHz turbo speed o Keyboard Interface o Supports 8086 interface o DRAM Controller for 120 ns/150 ns DRAM o Supports five 256K x 4 DRAM to achieve 640K on board without parity o Supports 256K x 1, 256K x 4, 1M x 1 DRAM o Supports mixed memory o 1.5 micron high performance CMOS technology o TTL compatible o 128 PQFP package **ACC83000 Model 30 Integrated Chip Set (MCA) c88 ***Info: ****General: The ACC 83000 chip set is designed for system designers to build 100% compatible IBM PS/2 Model 30 systems. The ACC 83000 contains two VLSI chips. The ACC 3100 provides system control signals, and the ACC 3000 is the I/O controller. The ACC 83000 supports a local CPU bus, a system memory bus, and compatible Model 30 buses. The system clock generates 24, 8 and 1.84 MHz clock timing. Up to eight I/O channel interrupts with sharing capability are available with variable wait states. ****ACC3000 I/O controller: The ACC 3000 is a VLSl device that emulates the I/O Support Gate Array of the IBM PS/2 Model 30. This chip is designed to help system designers build a Model 30 compatible machine at a lower cost with a faster design cycle. ****ACC3100 System Controller: The ACC 3100 is a VLSI device that emulates the System Support Gate Array of the IBM PS/2 Model 30. This chip is designed to help system designers build a machine compatible with the Model 30 at a lower cost and with a faster design cycle. ***Configurations: ACC 3000 I/O controller ACC 3100 System Controller ***Features: ****General: o 100% IBM PS/2 Model 30 system support gate array pin to pin compatible o 100% IBM PS/2 Model 30 I/O support gate array pin to pin compatible o Bus and memory controllers o Supports up to 8 channel interrupts with sharing capability o Wait state generator o System clock o Built-in mouse and keyboard interface o Decoder and data bus controller o NMI control and peripheral logic o Parallel port control o 1.5 micron high performance CMOS technology o 84-L PLCC package ****ACC3000 I/O controller: o 100% lBM Model 30 I/O support gate array pin-to-pin compatible o Controls the following chip select signals: Serial port Diskette controller Video controller Parallel port Fixed disk controller Real-time clock o NMI control logic o Peripheral sense logic and control o Built-in Model 30 keyboard and pointing device interface o Supports up to 8 channel interrupts with sharing capability o Provides parallel port control signals o Decoder & Data Bus controller o 1.5 micron high performance CMOS technology o 84-L PLCC package ****ACC3100 System Controller: o 100% IBM Model 30 system support gate array pin-to-pin compatible o Bus controller o Memory controller o Parity checker o Bus conversion logic o Wait state generator o System clock generator o DMA page registers and support logic o 1.5 micron high performance CMOS technology o 84-L PLCC package **ACC85000/A Model 50/60 Chipset (MCA) c88 ***Info: ****General: The ACC 85000 is a four-device CMOS chip set designed to provide OEMs with 100% PS/2 Model 50/60 compatibility and greater flexibility to build a distinctive high performance Model 50/60 compatible system. Only 29 external TTLs are required along with this highly integrated chip set to build a Model 50/60 compatible turbo system. The ACC 85000 chip set includes the ACC 5000 DMA and Micro Channel Controller, the ACC 5100 Peripheral Interface Controller, the ACC 5200 Data Buffer Logic and the ACC 5300 Memory Controller and Buffers. The ACC 5000 DMA and Micro Channel Controller integrates DMA control and Micro Channel control logic into a single chip. The ACC 5100 integrates a level-sensitive interrupt sharing controller, Programmable Option Select Logic, an 8254 compatible timer and glue logic. The ACC 5200 integrates data buffers and latches. The ACC 5300 integrates the memory controller, and memory buffers and latches. ****ACC 5000 DMA and Micro Channel Controller: The ACC 5000 is a high performance CMOS device that integrates the DMA control and Micro Channel control logic of an IBM PS/2 Model 50/60 into a single 144-pin flat pack. Both the DMA and Micro Channel operate at IBM standard clock rate to reach 100% lBM compatibility. The ACC 5000 supports turbo speed switch making the CPU speed switchable between turbo mode (12.5/16 MHz) and normal mode (10 MHz) on the fly. ****ACC 5100 Peripheral Interface Controller: The ACC 5100 is a high performance CMOS device that integrates a level-sensitive interrupt sharing controller, Programmable Option Select Logic, an IBM compatible timer, and glue logic into a single 144-pin flat pack. The ACC 5100 is one of four devices in the ACC 85000 chip set designed to provide 100% PS/2 Model 50/60 compatibility and greater flexibility in building a distinctive high performance Model 50/60 compatible system. ****ACC 5200 Data Buffer Logic: The ACC 5200 is a high performance CMOS device that integrates the data buffers and latches, and glue logic of a Model 50/60 compatible system into a 144-pin flat pack. The ACC 5200 is one of four devices in the ACC 85000 chip set designed to provide 100% PS/2 Model 50/60 compatibility and greater flexibility in building a distinctive high performance Model 50/60 compatible system. ****ACC 5300 Memory Controller and Buffers: The ACC 5300 is a high performance CMOS device that integrates the memory controller and memory buffers and latches of a Model 50/60 compatible system into a 144-pin flat pack. The ACC 5200 is one of four devices in the ACC 85000 chip set designed to provide 100% PS/2 Model 50/60 compatibility and greater flexibility in building a distinctive high performance Model 50/ 60 compatible system. ***Configurations: ACC85000 Chip Set consists of: ACC 5000 DMA and Micro Channel Controller ACC 5100 Peripheral Interface Controller ACC 5200 Data Buffer Logic ACC 5300 Memory Controller and Buffers 5000 + 5100 + 5200 + 5300 Variants: ACC85000A Chip Set No difference known. Datasheet seems to use terms "ACC85000A" and "ACC85000" interchangeably. ***Features: ****General: o 100% hardware and software compatible with IBM PS/2 Model 50/60 o 100% compatible with IBM PS/2 Model 50/60 Micro Channel implementation o Supports 10, 12.5, and 16 MHz 80286 and 803868X processors o DMA and Micro Channel operate at the ultimate Micro Channel bus performance o Software switching for turbo speed o Compatible with commercially available VGA chips o Supports up to 16 MB of on-board DRAM o Supports 256K x1, 256K x 4, 1M x 1, and 1M x 4 DRAMs o Supports shadow RAM o Supports EMS 4.0 ****ACC 5000 DMA and Micro Channel Controller: o 100% IBM PS/2 compatible Model 50/60 DMA controller implementation o 100% IBM PS/2 compatible Model 50/60 Micro Channel implementation o Supports 10, 12.5, and 16 MHz 80286 and 80386SX processors o 200 ns cycle for DMA and Micro Channel provides the ultimate Micro Channel BUS performance o Turbo speed change accomplished through software switching on the fly o Equivalent performance of two 8237 DMA controllers with support for Extended mode o 16 MB memory address capability and 64 KB I/O address capability o Eight independent DMA channels for extended mode o Executes central arbitration control point functions o Regulates and controls the duration of arbitration cycles o Monitors the Micro Channel for time-out conditions o Clock and reset logic o 1.5 micron high performance CMOS technology o 144-pin PFP package ****ACC 5100 Peripheral Interface Controller: o 100% hardware and software compatible with IBM PS/2 Model 50/60 o 100% implementation of Programmable Option Select (POS) logic o 100% implementation of Model 50/60 compatible system control registers o Two IBM compatible interrupt controllers o IBM compatible system timer o Watchdog timer logic o System board I/O decode logic o Peripheral device control logic o NMI generator o Clock generation logic for the 80287 and 8042 keyboard controller o Supports external CMOS RAM for configuration registers o Built-in 74L8245 compatible video buffers o 1.5 micron high performance CMOS technology o 144-pin PFP package ****ACC 5200 Data Buffer Logic: o 100% hardware and software compatible with lBM PS/2 Model 50/60 o CPU clock rates up to 20 MHz o Micro Channel data buffers and latches o 24 milliamp output drive capability on SD0-15 bus outputs o Memory parity generation and detection o Compatible with commercially available VGA interface o Local bus data latches o 1.5 micron high performance CMOS technology o 144-pin PFP package ****ACC 5300 Memory Controller and Buffers: o 100% hardware and software compatible with the IBM PS/2 Model 50/60 o Micro Channel address buffers and control latches o EPROM and DRAM control logic o Refresh logic o Supports 256K x 1, 256K x 4, 1M x 1, and 1M x 4 o Supports up to 16 MB of on-board RAM o Supports shadow RAM o Supports EMS 4.0 o 1.5 micron high performance CMOS technology o 144-pin PFP package **ACC1000 Turbo PC/XT Integrated Bus and Peripheral Ctrl. 04/02/88 ***Info: The ACC 1000 is a high performance CMOS PC/XT bus and peripheral controller for designers to build a PC BUS-compatible single-board computer with "turbo" power. The ACC 1000 replaces most TTL/SSI/MSI devices including six Intel peripheral controller ICs required to build a typical Turbo XT. The LED output which indicates running frequency is supported by the ACC 1000. The ACC 1000 integrates all the controller functions of a typical "Turbo/XT" high performance motherboard. This high integration not only increases system performance but also reduces the total system cost because of lower power requirements. increased reliability, and reduced components and board size. ***Configurations: ACC1000 ***Features: o 100% hardware and software compatible with IBM PC/XT o Fully compatible with Intel's 8284 Clock Generator 8288 Bus Controller 8237 DMA Controller 8259 Interrupt Controller 8254 Timer/Counter o 8255 compatible peripheral I/O port o Built-in parity generator and checker, wait state logic, and NMI control logic o Built-in ROM decoder for 2764/27256 o Built-in RAM decoder for 4164/41256 o Supports both 9.54 MHz and 4.77 MHz system clock with a single common crystal o System clocks switchable by both software and hardware on the fly o Keyboard Interface o Memory Controller o Supports LED output to indicate running frequency o 640K total memory support o 1.5 micron high performance CMOS technology o TTL compatible o 84-L PLCC package **ACC2036 Single Chip Solution 2036 (286/386SX)