| 
 Cyrix CPU Detection Guide
         Preliminary
        Revision 1.01
 
?1997 Cyrix
Corporation. All Rights Reserved.
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  states nor implies any representations or warranties of any
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 Trademarks 
 Cyrix, the Cyrix logo, and
combinations thereof are trademarks of Cyrix Corporation. 
 5x86, 6x86, 6x86MX, MediaGX are
registered trademarks of Cyrix Corporation. 
 MMX is a trademark of Intel
Corporation. 
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Revision History 
	
	
	 
	  
    	| REVISION | 
    RELEASE DATE | 
    DESCRIPTION OF CHANGES | 
   
  
    | 1.00 | 
    09/30/97 | 
    First Release (preliminary). | 
   
  
    | 1.01 | 
    10/02/97 | 
    Corrected the GXm and MediaGX values for DIR0 lookups | 
   
  
    | ?/FONT> | 
    ?/FONT> | 
    ?/FONT> | 
	   
	 
	
	
Cyrix CPU
Detection 
 Introduction 
 This document provides an overview
of the three possible methods for detecting a Cyrix CPU. Once the
correct method is identified (flowchart below), each detection
method is covered in detail. This includes: How to detect the
Cyrix CPU; Which CPU is present; What is the standard feature
set; What are the Cyrix specific features.
 The three CPU detection methods are: 
 1. CPUID - Standard Levels 
 This method provides the standard
feature set (not vendor specific feature such as Extended MMX)
and requires a look-up table. 
 2. CPUID - Extended Levels 
 This is the preferred method of
detection because it provides the ability to get the CPU name
without requiring a look-up table. It also provides information
that may be Cyrix specific. The CPUID - Extended Levels are only
supported in the most recent CPUs such as GXm. 
 3. The 5/2 Method 
 This method is used for older CPUs
that do not support CPUID such as the 486DLC, 486SLC, 486DX,
486DX2 etc. 
 The flowchart below should be used
to determine the correct detection method. After identifying
which method to use, refer to the correct section for further
explanation. 
  
 
 CPUID - Standard
Levels 
 Overview 
 The CPUID instruction is an
application level (ring 3) instruction that provides information about the
system's processor and its feature set. The CPUID instruction
provides multiple functions, each containing different information
about the processor. The CPUID instruction is used to identify
the vendor, family, and type of processor, as well as information
about any special features, like MMX™, that the processor
may support. The CPUID instruction may be executed at any
privilege level.  
 Testing for CPUID Support 
 In order to avoid an invalid opcode
exception on processors that do not support the CPUID
instruction, software must first verify that the processor
supports the CPUID instruction. The presence of the CPUID
instruction is indicated by the ID bit (bit 21) in the EFLAGS
register. If this bit can be toggled, the CPUID instruction is
present and enabled on the processor. The following sample code
will check for the presence of the CPUID instruction. The following 
code should be executed after support for EFLAGS is verified or at
least a 80386/80486 is known to be present. 
   Sample Code 
	
 
  	
		| pushfd | ; get extended flags |  
  	
		| pop eax | ; store extended flags in eax |  
  	
		| mov ebx, eax | ; save current flags |  
  	
		| xor eax, 200000h | ; toggle bit 21 |  
  	
		| push eax | ; put new flags on stack |  
  	
		| pushfd | ; get extended flags |  
  	
		| pop eax | ; store extended flags in eax |  
  	
		| xor eax, ebx | ; if bit 21 r/w then eax <> 0 |  
  			| popfd | ; flags updated now in flags |  
		| je no_cpuid | ; can't toggle id bit (21) no cpuid here |  
 
	
Standard CPUID Levels 
 Each of the standard CPUID levels
(EAX = 0 and EAX = 1) contain the same information for all vendors.
The higher CPUID levels, including the extended levels, report
information that is specific to the Cyrix family of processors. 
 Table 1 summarizes the actual CPUID
values currently returned by Cyrix processors.  
 Table 1. Actual CPUID Result
Values: 
	
	 
	  
    | Description | 
    6x86  | 
    6x86 (4.x) | 
    MediaGX | 
    6x86MX | 
    GXm | 
   
  
    | Standard Levels 1 | 
    1 | 
    1 | 
    1 | 
    1 | 
    2 | 
   
  
    | Stepping | 
    xx | 
    xx | 
    xx | 
    0 | 
    0 | 
   
  
    | Model | 
    2 | 
    2 | 
    4 | 
    0 | 
    4 | 
   
  
    | Family | 
    5 | 
    5 | 
    4 | 
    6 | 
    5 | 
   
  
    | Type | 
    0 | 
    0 | 
    0 | 
    0 | 
    0 | 
   
  
    | Extended Levels 2 | 
    - | 
    - | 
    - | 
    - | 
    8000 0005h | 
   
  
    | TLB Info 3 | 
    - | 
    - | 
    - | 
    - | 
    00 00 70 01h | 
   
  
    | Cache Info 3 | 
    - | 
    - | 
    - | 
    - | 
    00 00 00 80h | 
   
 
	
	
1 EAX Value when CPUID (EAX = 0) Executed 
2 Extended CPUID - EAX = 8000 0000h 
3 EAX = 2; See Table 5 for Value Definitions 
(EAX = 0h) - Vendor String and Max
Standard CPUID Levels Supported 
 Standard function 0h (EAX = 0) of
the CPUID instruction returns the maximum standard CPUID levels
supported by the current processor in EAX. EBX through EDX return
the vendor string of the processor. Please make note of the order
of the registers. 
	
	 
  
    | EAX | 
    Max Standard Levels | 
   
  
    | EBX | 
    Vendor ID String 1 | 
   
  
    | ECX | 
    Vendor ID String 3 | 
   
  
    | EDX | 
    Vendor ID String 2 | 
  		 
	 
	
(EAX = 01h) - Processor Signature and
Standard Feature Flags 
 Standard function 01h (EAX = 1) of
the CPUID instruction returns the Processor Type, Family, Model,
and Stepping information of the current processor in EAX. The
Standard Feature Flags supported are returned in EDX. The other
registers upon return are currently reserved. The breakdown of
the EAX register is as follows: 
	
	
	 
	  
	    | EAX[3:0] | 
    Stepping ID | 
   
  
    | EAX[7:4] | 
    Model | 
   
  
    | EAX[11:8] | 
    Family | 
   
  
    | EAX[15:12] | 
    Type | 
   
  
    | EAX[31:16] | 
    Reserved | 
   
  
    | EBX | 
    Reserved | 
   
  
    | ECX | 
    Reserved | 
   
  
    | EDX | 
    Standard Feature Flags | 
	   
	 
	
	
(EAX = 02h) - TLB and L1 Cache
Information  
 Standard function 02h (EAX = 02h) of
the CPUID instruction returns information that is specific to the
Cyrix family of processors. Information about the TLB is returned
in EAX. Information about the L1 Cache is returned in EDX. This
information is to be looked up in a lookup table. (See Table 5) 
	
	 
	  
    | EAX | 
    TLB Information | 
   
  
    | EBX | 
    Reserved | 
   
  
    | ECX | 
    Reserved | 
   
  
    | EDX | 
    L1 Cache Information | 
	   
	 
	
Standard Feature Flags 
 The standard feature flags are
returned in the EDX register when the CPUID instruction is called
with standard function 01h (EAX = 1). Each flag refers to a
specific feature and indicates if that feature is present on the
processor. Some of these features require enabling or have
protection control in CR4. Table 2 summarizes the standard
feature flags. 
 Before using any of these features
on the processor, the software should check the corresponding
feature flag. Attempting to execute an unavailable feature can
cause exceptions and unexpected behavior. For example, software
must check bit 4 before attempting to use the Time Stamp Counter
instruction. See the glossary for a definition of each feature. 
 Table 2 - Standard Feature
Flags Values: 
	
	
	 
	  
    | Feature Flag | 
    EDX Bit | 
    CR4 Bit | 
    6x86* | 
    6x86* (4.x) | 
    MediaGX* | 
    6x86MX | 
    GXm | 
   
  
    | FPU | 
    0 | 
    - | 
    X | 
    X | 
    X | 
    X | 
    X | 
   
  
    | V86 | 
    1 | 
    0,1 | 
    - | 
    - | 
    - | 
    - | 
    - | 
   
  
    | Debug | 
    2 | 
    3 | 
    - | 
    X | 
    - | 
    X | 
    - | 
   
  
    | Page Size | 
    3 | 
    4 | 
    - | 
    - | 
    - | 
    X | 
    - | 
   
  
    | Time Stamp Counter | 
    4 | 
    2 | 
    - | 
    - | 
    - | 
    X | 
    X | 
   
  
    | RDMSR/ WRMSR | 
    5 | 
    8 | 
    - | 
    - | 
    - | 
    X | 
    X | 
   
  
    | PAE | 
    6 | 
    5 | 
    - | 
    - | 
    - | 
    - | 
    - | 
   
  
    | MC Exception | 
    7 | 
    6 | 
    - | 
    - | 
    - | 
    - | 
    - | 
   
  
    | CMPXCHG8B | 
    8 | 
    - | 
    - | 
    X | 
    - | 
    X | 
    X | 
   
  
    | APIC on Chip | 
    9 | 
    - | 
    - | 
    - | 
    - | 
    - | 
    - | 
   
  
    | Reserved | 
    10-11 | 
    - | 
    - | 
    - | 
    - | 
    - | 
    - | 
   
  
    | MTRR | 
    12 | 
    - | 
    - | 
    - | 
    - | 
    - | 
    - | 
   
  
    | Global Bit | 
    13 | 
    7 | 
    - | 
    - | 
    - | 
    X | 
    - | 
   
  
    | Machine Check | 
    14 | 
    - | 
    - | 
    
	
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