AMD K7
| General Details | Name | Athlon | |
| Codename | Argon, K7 | ||
| Family/Generation | 80686, 7th Generation, MMX, SSE (partial) | ||
| Vendor | AMD | ||
| Manufacturer | AMD | ||
| First Introduction |
Oct 13, 1998 (MPF: 500 MHz Samples) Jun 23, 1999 (500, 550, and 600 MHz) Aug 9, 1999 (650 MHz) |
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| Physical Details | Package Type |
242 Contact Slot A Cartridge 575 Pin BGA |
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| Package Size |
13.99 cm x 6.27 cm x 1.64 cm (Slot A Cartridge) 3.10 cm x 3.10 cm x 0.20 cm (BGA) |
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| Socket or Slot | Slot A | ||
| Transistors | 22,000,000 (includes 152 KB L1 Cache) | ||
| Process Technology | 6Mi, 0.25 µm, CMOS | ||
| Die Size | 184 mm² | ||
| Electrical Details | Split Voltage | N/A | |
| Core Voltage | 1.6 V | ||
| L2 Voltage |
3.3 V 2.5 V |
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| I/O Voltage | 1.6 V | ||
| Typical Power |
500 MHz: 38 W 550 MHz: 41 W 600 MHz: 45 W 650 MHz: 48 W |
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| Maximum Power |
500 MHz: 42 W 550 MHz: 46 W 600 MHz: 50 W 650 MHz: 54 W |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed | 500, 550, 600, 650 MHz | |
| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1/3x, 1/2x, or 2/3x Core Speed | ||
| External Bus Speed |
100 MHz Double-Data Rate, DEC Alpha EV6 Protocol, up to 24 Outstanding Transactions per Processor |
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| Core/Bus Ratio | 5.0x, 5.5x, 6.0x, 6.5x | ||
| Miscellaneous | usual Motherboard | Single or Dual Processor Slot A | |
| usual Chipset | AMD 751/756, AMD 752/756, or non-AMD | ||
| Pictures |
0.25 µm Die (364 KB JPG) 0.25 µm FPU Die (34 KB JPG) BGA Top (27 KB JPG) and Bottom (68 KB JPG) |
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| Processor Core | Generic Details | RISC, Out-of-order and Speculative Execution | |
| Specific Details |
72 MOP Entry ROB/ICU 18 MOP Entry Integer Scheduler 36 MOP Entry FP Scheduler |
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| Registers |
32 Bit Integer, 80 Bit FP, 64 Bit MM 24 Entry 32 Bit 9xRead 8xWrite IFFRF (Integer RAT) 88 Entry 90 Bit 5xRead 5xWrite FPRF (FP RAT) |
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| Pipeline Depth | 10 (Integer), 15 (FP) | ||
| Instruction Decoder |
Direct and Vector Path up to 3x IA-32/Cycle up to 3x MOPs/Cycle up to 6x ROPs/Cycle |
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| Execution Units |
3x IEU (2x w/ MUL, 1x w/o MUL), 3x AGU (1x/IEU), 3x Pipelined FP (1x ADD, 1x MUL, 1x STORE) |
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| Execution Speed |
up to 3x Integer MOPs/Cycle up to 6x Integer ROPs/Cycle up to 3x FP ROPs/Cycle |
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| Processor Buses | Address/Request Bus Width | 13 Bit | |
| Snoop Bus Width | 13 Bit | ||
| Data Bus Width | 64+8 Bit, separate 64+8 Bit Backside L2 Cache Bus | ||
| Physical Memory | 2^43 Bit = 8 TB | ||
| Virtual Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | SMP, up to 14 Processors | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
64 KB, 2-Way, 64 Byte/Line, SI, LRU, 3 Pre-decode Bits/Byte (adds 24 KB) |
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| Data |
64 KB, 2-Way, 64 Byte/Line, MOESI, LRU, Dual-ported, Write-Allocate, Multi-banked |
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| Level 2 | Unified |
512 KB..8 MB, 64 Byte/Line On-Die Tags for 512 KB 2-Way (512 KB, 1 MB, or 2 MB) Direct-Mapped (4 MB and larger) |
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| Processor Buffers | Buffers |
2x I-miss Address 6x D-miss Address 8x Victim Address 8x Snoop Address 4x Write Address |
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| Load/Store Queue |
12 Entries for L1 Cache 32 Entries for L2 Cache and Memory |
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| Prefetch Queue |
16 Byte/Cycle from Fetch to Scan Stage 3x 8 Byte Queue in Direct Path Decoder |
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| Branch Prediction | Static | Yes | |
| Dynamic | 2,048 Entry BHT, 2-Bit Smith Algorithm | ||
| 2,048 Entry BTAC | |||
| RSB | 12 Entries | ||
| TLB | 4 KB Code L1 | 16 Entries, Fully, LRU | |
| 4/2 MB Code L1 | 8 Entries, Fully, LRU | ||
| 4 KB Data L1 | 24 Entries, Fully, LRU | ||
| 4/2 MB Data L1 | 8 Entries, 4-Way, LRU | ||
| 4 KB Code L2 | 256 Entries, 4-Way, LRU | ||
| 4/2 MB Code L2 | n/a | ||
| 4 KB Data L2 | 256 Entries, 4-Way, LRU | ||
| 4/2 MB Data L2 | n/a | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX, 3DNow!, Extended 3DNow!, SSE-MMX, SSE-MEM | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
